Synopsys Design and Verification Engineer Salaries - Browse Average Salaries by Location
Browse Synopsys Salaries by Job Title →Updated
What is the average salary of Synopsys Design and Verification Engineer?
Synopsys Design and Verification Engineers earn $51,000 annually, or $25 per hour, which is 48% lower than the national average for all Design and Verification Engineers at $83,000 annually and 26% lower than the national salary average for all working Americans. The highest paid Design and Verification Engineers work for Cisco Systems at $101,000 annually and the lowest paid Design and Verification Engineers work for Atria Logic at $68,000 annually.
What is the salary for Design and Verification Engineer at Synopsys?
The salary for Design and Verification Engineer at Synopsys is $51,000 annually.
What company pays the highest salary for the Design and Verification Engineer position?
Cisco Systems pays the highest salary for the Design and Verification Engineer position at $101,000 annually.
What company pays the lowest salary for the Design and Verification Engineer position?
Atria Logic pays the lowest salary for the Design and Verification Engineer position at $68,000 annually.
-
Audio Visual Technical R&D Engineer
Norcross, GA - $75,000 - $100,000 per year
Update your browser to have a more positive job search experience.
Upgrade My Browser