428 ASIC Verification Engineer Jobs Nationwide

* Perform Requirements based Verification of FPGAs/ASICs using SystmVerilog UVM * Understand design requirements and specifications in coordination...

NOTE: Due to nature of the project, U.S. Citizenship is required. Resource will work onsite from day one at Cedar Rapids, IA (5 days onsite) Experience...

Strong expertise along with complex SoC/IP debug is a must * At-least 5+ years of experience in System Verilog HVL * Experience in complete verification...

* Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area...

We are looking for SOC Design Verification Engineer who can work 100% Onsite at Santa Clara CA. Candidate should be able to define and implement...

* Develop and execute UVM testbenches for complex ASIC/SOC designs. * Verify high-speed I/O interfaces (PCIe, USB, Ethernet) and CPU subsystems...

We are seeking a skilled and motivated Electrical Engineer to join our engineering team in the aviation industry. This position will be responsible...

As the Head of Semiconductor Sales Practice at Capgemini Engineering, you will lead the sales and Industry SME teams for a global product engineering...

* Self-starter who requires minimal oversight * Experience with Siemens Physical Verification tools and methods * Radiation effects analysis...

An innovative, well-capitalised semiconductor company is seeking a Mixed Signal Verification Engineer to support the development of next-generation...

NOTE: HAPS or EMULATION – Engineer should aware Model build and DESIGN along with integration and development. What candidate will Be Doing: * Map...

We are looking for SOC Design Verification Engineer who can work 100% Onsite at Seattle WA. Candidate should be able to define and implement SoC...

Prefer experience with PSS language and UVM. JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores...

* Technical lead for full chip and/or blocks level verification * Define verification plan in co-ordination with Architects, Logic and Mixed...

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible...

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible...

* Lead design and development of electrophysiological systems devices. * Implement Wi-Fi protocols for seamless data transfer and connectivity...

Not sure what skills you will need for this opportunity Simply read the full description below to get a complete picture of candidate requirements...

Technical lead for full chip and/or blocks level verification Define verification plan in co-ordination with Architects, Logic and Mixed-signal...

Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband...